1. Field of the Invention
The present invention relates to a memory module, and more particularly, to a memory module with improved data bus performance.
2. Description of the Related Art
Memory devices continue to evolve, with the focus being on high density and large capacity based on high density. At the same time, central processing units (CPU) of computer systems continue to undergo development, with the focus being high-speed. As a result, in computer systems, it is common for the difference in operating speed between the CPU and the memory device to be large; so large, that in contemporary systems, the operating speed of the memory device is typically the primary factor in restricting overall system performance.
In order to improve system operating speed, high-speed memory devices and high-performance memory systems are under development. In high-performance memory systems the goal is to process input/output data within a given unit time. For such high-speed memory systems, firstly, the high-speed memory device must be developed, and secondly, module and bus architectures enabling high-speed of an input/output interface for interconnecting the memory device and the exterior of the memory device are also very important.
In general, a conventional bus architecture of the memory systems is classified into a stub-form and a loop-through form. FIG. 1 is a diagram illustrating a conventional stub-form memory bus architecture, and FIG. 2 is a diagram illustrating a conventional loop-through form memory bus architecture.
Referring to FIG. 1, in the conventional stub-form memory bus architecture, a bus 11 is provided on a system board, and each memory device 15 on a memory module 13 coupled to the system board is connected to the bus 11 through a stub 17 on the module 13. The stub 17 diverges from the bus 11 through a module socket 19.
Referring to FIG. 2, in the conventional loop-through form memory bus architecture, each memory device 25 on a memory module 23 is consecutively directly connected to a bus 27 on the module 23 without a stub. The bus 27 on the module 23 is connected to a bus 21 located on a system board through a module socket 29.
In FIGS. 1 and 2, the buses 11 and 21 are connected to memory controllers 10 and 20.
In the conventional stub-form bus architecture of FIG. 1, since the entire length of a channel, that is, the entire length of the bus 11 is relatively short, signal transmission delay time through the channel is likewise short, and, therefore, electron wave interference is small. However, due to the stub architecture, discontinuity and impedance mismatching occur on the channel, and as a result, reflected wave noise is generated. As a result, during high-speed operation, due to the effect of the reflected wave noise, serious distortion occurs in the waveform of a signal on the channel. That is, in the stub-form bus architecture, due to the reflected wave noise on the channel, signal integrity deteriorates.
Thus, in the stub-form bus architecture, in order to improve signal integrity, a stub resistance is provided on the bus. As a result of the increased resistance, the driving voltage of a driver in the memory controller 10 and the driving voltage of a driver in the memory device 15 are also increased, and therefore, power consumption is increased.
Meanwhile, in the conventional loop-through form bus architecture of FIG. 2, since the entire channel consisting of the bus 21 located on the system board and the bus 27 on the module 23 has an uniform impedance, impedance mismatching is reduced, and thus, reflected wave noise is greatly reduced, as compared to the stub-form. Also, since the stub and the stub resistance are not required in the above architecture, the driving voltage of a driver in the memory controller 20 and the driving voltage of a driver in the memory device 25 are relatively smaller, and thus, power consumption is reduced.
Arising from the above advantages in the loop-through form bus architecture, it is generally evident that the loop-through form bus architecture of FIG. 2 is more suitable for a high-speed operation, as compared to the stub-form bus architecture of FIG. 1. However, as known from FIG. 2, in the loop-through form bus architecture, the length of the entire channel is very long, as compared to the conventional stub-form bus architecture of FIG. 1. As a result, the signal transmission delay time on the channel is long, and the electron wave interference is large, and, as a consequence, high-speed performance is restricted. Also, in the loop-through form of FIG. 2, relatively more memory devices are mounted on the channel, as compared to the stub-form of FIG. 1. Thus, capacity load is increased, and the impedance of the channel is reduced. The low impedance of the channel is a factor contributing to increased costs for fabricating systems such as a printed circuit boards (PCBs) and a module connectors.
To address the above limitations, it is an object of the present invention to provide a memory module, which is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced, and then, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a printed circuit board (PCB) and a module connector can be reduced.
Accordingly, to achieve the above object, there is provided a memory module in which a plurality of memory devices are mounted. The memory module includes a plurality of tabs located on one side of the front and on one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias, in which at least one memory device is connected to each of the data buses.
Each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.
According to a first preferred embodiment of the present invention, the memory module further includes a control/address bus extended from the tabs on the front of the memory module to the tabs on the rear of the memory through one of the vias, and a control/address stub diverged from a point of the control/address bus and commonly connected to the memory devices.
In the first embodiment, the memory module further includes a buffer or a register for driving the control/address stub at the diverged point. Also, in the first embodiment, preferably, the control/address stub is formed to be parallel with one side of the memory module on which the tabs are formed, and the control/address bus is formed to be perpendicular to one side of the memory module on which the tabs are formed.
According to a second preferred embodiment of the present invention, the memory module further includes control/address bus extended from the tabs on the front of the memory module to the tabs on the rear of the memory through one of the vias, a first control/address stub diverged from a point of the control/address bus and commonly connected to memory devices, which is mounted on the front of the memory module, and a second control/address stub diverged from a point of the control/address bus and commonly connected to memory devices, which is mounted on the rear of the memory module.
In the second embodiment, the memory module further includes a buffer or a register for driving the first control/address stub at the diverged point and a buffer or a register for driving the second control/address stub at another diverged point. Also, in the second embodiment, preferably, the first and second control/address stubs are formed to be parallel with one side of the memory module on which the tabs are formed, and the control/address bus is formed to be perpendicular to one side of the memory module on which the tabs are formed.
According to a third preferred embodiment of the present invention, the memory module further includes control/address bus extended from the tabs on the front of the memory module to the tabs on the rear of the memory through one of the vias, and a control/address stub diverged from a point of the control/address bus, in which the memory devices mounted on the front of the memory module and the memory devices mounted on the rear of the memory module are commonly connected to control/address stub.
In the third embodiment, the memory module further includes a buffer or a register for driving the control/address stub at the diverged point. Also, in the third embodiment, preferably, the control/address stub is formed to parallel with one side of the memory module on which the tabs are formed, and the control/address bus is formed to be perpendicular to one side of the memory module on which the tabs are formed.
According to a fourth preferred embodiment of the present invention, the memory module further includes control/address bus formed in a loop-through shape and extended from one pin of the tabs to another pin of the tabs and commonly connected to the memory devices.
In the fourth embodiment, preferably, the control/address bus is formed to be parallel with one side of the memory module on which the tabs are formed.
According to a fifth preferred embodiment of the present invention, the memory module further includes control/address bus formed in a loop-through shape passing the front and rear of the memory module through the vias and extended from one pin of the tabs to another pin of the tabs, and the memory devices mounted on the front of the memory module and the memory devices mounted on the rear of the memory module are commonly connected to the control/address bus.
In the fifth embodiment, preferably, the control/address bus is formed to be parallel with one side of the memory module on which the tabs are formed.
In alternative embodiments, one of the plurality of data buses and the control/address bus may be configured in a short loop-though configuration, while the other is configured in a stub configuration.